tgss-mem

Memory #109 CURRENT

FPGA — Colorlight 5A-75B / ECP5 FPGA dev board received 2026-04-22; Colorlight 5A-75B classic revision, Lattice ECP5 LFE5U-25F, dual GbE, open Yosys toolchain; not in existing synthesis spec's Zynq-only list **Board received 2026-04-22:** Colorlight 5A-75B (classic revision — *not* the 5A-75B+ which ships with the LFE5U-45F). Bought via Amazon reseller "MiiElAOD". **Confirmed spec:** | | | |---|---| | FPGA | Lattice ECP5 **LFE5U-25F-6BG256C** (24k LUTs, 108 KB BRAM, 2 PLLs) | | Ethernet | **Dual GbE PHYs** (originally IN+OUT for LED panel daisy-chaining — both usable) | | SDRAM | 8 MB (Winbond W9825G6KH or equivalent) | | SPI flash | 4 MB (Winbond W25Q32) | | CPU | None — pure FPGA. Softcore (VexRiscv / PicoRV32) if needed. | | Toolchain | **Fully open source**: Yosys + nextpnr-ecp5 + prjtrellis. oss-cad-suite bundles all. No Vivado / Quartus required. | | Programmer | OpenOCD or ecpprog via USB-JTAG | | Unit cost | ~$20–25 USD | **Why:** - Fits Lydian's "sovereign mathematics" ethos — fully open toolchain, no proprietary vendor binaries in the build chain, reproducible synthesis. - Dual GbE enables real LCF-over-Ethernet experiments, not just simulation. - Cheap enough to stand up 6+ boards for a physical Six-Hop Theorem demo. **How to apply:** - **Not yet added to `TTI_FPGA_SYNTHESIS_SPEC_V1.md`** (that doc enumerates 7 Zynq/Intel boards — this is an 8th, open-toolchain path). Update pending. - LUT budget (24k) is tight — full TCHAS-AEAD-GZ pipeline will need time-multiplexing or a scaled-down form. Early modules (`five_state_element.sv` < 100 LUTs, `teu_unit.sv` < 1k, `cascade_word.sv` < 10k) fit comfortably and are the right first-test scope. - `sysDSP` block count is limited; watch multiplier counts when porting anything from the Zynq-sized Tribernachi multiply. - First validation step (Day 1): IDCODE detect via `openFPGALoader --detect` or `ecpprog -t` to confirm the chip is indeed LFE5U-25F. - Ethernet from the dev PC is now DHCP-configured on 192.168.0.x (switched 2026-04-22) so the board can plug into the same router and be on the same subnet. **Board confirmed revision (2026-04-23):** V8.2 (silkscreen). Dual RJ45 (RJ1, RJ2) confirmed — memory spec accurate. FPGA covered by Colorlight branding sticker; BG256 row letters `A–T` (skipping I, O) visible on silkscreen, confirms BG256C package. **JTAG test pads (2026-04-23) — critical:** four unpopulated through-holes in a row directly above the FPGA BGA on the top side, labeled individually in silkscreen. Left-to-right from component-side view: - **J32** → **TCK** - **J30** → **TDI** - **J31** → **TDO** - **J27** → **TMS** - **GND**: not at this cluster — use screw terminal GND or any HUB75 IDC frame GND. Mapping follows Tom Verbeure's 5A-75B V7.0 reverse-engineering, assumed consistent on V8.2 but unverified by IDCODE yet. If IDCODE detect fails, swap pairs: TDI↔TDO first, then TCK↔TMS. **Programmer selected (2026-04-23):** CJMCU FT232H USB-to-GPIO/SPI/I2C breakout (positive-ID'd by silkscreen "VCORE FT232H USB to GPIO+SPI+I2C"). MPSSE mapping: AD0=TCK, AD1=TDI, AD2=TDO, AD3=TMS. openFPGALoader cable name: `ft232`. Windows requires Zadig driver swap to WinUSB before libusb access works. Treedix kept as alternate; FT2232H Mini-module ordered as backup. **Physical wire colors as installed (2026-04-27):** Mark soldered four colored wires to J27/J30/J31/J32: - Black → J27 - White → J30 - Yellow → J31 - Red → J32 - Plus a 5th GND wire to the screw-terminal negative. **JTAG attempt outcome (2026-04-27 evening):** All 6 sensible permutations of TCK/TDI/TDO/TMS across these four wires *failed* with "TDO is stuck at 0" using `openFPGALoader --cable ft232 --detect`. **Conclusion: J27/J30/J31/J32 are NOT routed to the ECP5 JTAG TAP on V8.2.** Tom Verbeure's V7.0 mapping does not carry over to V8.2 — those four pads on V8.2 connect to user-fabric pins (likely LED panel signals or similar). The wires can stay soldered; they don't conflict with the new plan. **Diagnostic data points worth retaining:** - Voltage probe (board powered, FT232H disconnected): J27 (Black) = floating; J30/J31/J32 (White/Yellow/Red) = all 3.3V. Looked like a JTAG header (1 TCK floating + 3 pull-ups for TMS/TDI/TDO) but the permutation sweep proved otherwise. - FT232H verified working via AD1↔AD2 loopback (TDI→TDO short): "TDO stuck at 0" disappeared from output → programmer side is fine, board side is the unreachable path. - The "Can't read iSerialNumber field from FTDI: considered as empty string" warning is cosmetic and does not affect JTAG functionality. Do *not* reprogram the FT232H EEPROM — bricks the programmer for no benefit. **Pivot — direct SPI flash programming via U31 (2026-04-27, resume 2026-04-29 Wed):** - U31 = Winbond W25Q32 SOIC-8 (confirmed visually, between dual GbE PHYs, directly above J27–J32 pads). - Tool needed: SOIC-8 test clip (Pomona 5250 or clone). Mark ordered Amazon overnight 2026-04-27 evening; resume Wednesday 2026-04-29 (full day Tuesday 2026-04-28 unavailable). - Wiring map for openFPGALoader `--bus spi` mode (FT232H, same MPSSE pin assignments as JTAG mode): - AD0 → CLK (W25Q32 pin 6) - AD1 → DI/MOSI (pin 5) - AD2 → DO/MISO (pin 2) - AD3 → /CS (pin 1) - GND → GND (pin 4) - 3.3V (FT232H) → VCC (pin 8) — board powered OFF for clip programming - /WP (pin 3) and /HOLD (pin 7) left floating (chip has internal pulls) - Pin 1 orientation: dot in lower-left corner of chip body when text is upright. - First command: `openFPGALoader --cable ft232 --bus spi --detect` — should report W25Q32 JEDEC ID 0xEF4016 if clip is making good contact. - Then: `openFPGALoader --cable ft232 --bus spi --write-flash bitstream.bit` to program. **Backup hardware on hand (2026-04-27):** DAP-Link V2 (real CMSIS-DAP probe based on Cortex-M0+, USB-C). NOT directly usable with openFPGALoader for ECP5 — would require OpenOCD `cmsis-dap` driver path. Keep as last-resort fallback only; SPI flash via clip is the better pivot. **Lesson:** When the user is about to act on a hardware mapping I'm giving from memory, *check the existing memory file first* before answering. (See `feedback_check_memory_first.md`.) — [project_fpga_colorlight.md]

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